This invention relates generally to electronic memories and particularly to electronic memories that use phase change material.
Phase change materials may exhibit at least two different states. The states may be called the amorphous and crystalline states. Transitions between these states may be selectively initiated. The states may be distinguished because the amorphous state generally exhibits higher resistivity than the crystalline state. The amorphous state involves a more disordered atomic structure. Generally any phase change material may be utilized. In some embodiments, however, thin-film chalcogenide alloy materials may be particularly suitable.
The phase change may be induced reversibly. Therefore, the memory may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter, or vice versa, in response to temperature changes. In effect, each memory cell may be thought of as a programmable resistor, which reversibly changes between higher and lower resistance states. The phase change may be induced by resistive heating.
In some embodiments, the cell may have a large number of states. That is, because each state may be distinguished by its resistance, a number of resistance determined states may be possible, allowing the storage of multiple bits of data in a single cell.
A variety of phase change alloys are known. Generally, chalcogenide alloys contain one or more elements from Column VI of the periodic table. One particularly suitable group of alloys is the GeSbTe alloys.
Existing phase change memories utilize bipolar transistors as isolation elements. The bipolar transistors are advantageous since they can provide relatively high programming current. Generally the bipolar transistor has its emitter tied to one terminal of the phase change memory element and its base tied to the respective row line while its collector is tied to a common substrate ground. The other terminal of the phase change memory element may be tied to its respective column. The bipolar transistor is conductive for programming or reading and is in the off state and possibly reverse biased for all other circumstances.
In particular, to program a one level, a selected column is brought to a voltage level equivalent to the one level programming voltage while unselected columns are brought to zero volts. The selected row is brought to zero volts and the unselected rows are both brought to the programming voltage or higher. Thus, when the column is brought high, the corresponding selected row has zero volts on it and as a result, current flows into the phase change memory cell.
Conversely, the unselected column has a zero volt bias and the unselected row has a programming voltage applied to it. All unselected memory elements thus have their emitter base either reverse biased or zero volt biased, assuring the bipolar transistors are turned off. All selected memory elements have their emitter base forward biased allowing appropriate current to flow through the phase change material.
One concern that arises with the bipolar isolation scheme is the large number of reverse biased emitter base junctions. All isolation elements except those on selected rows and columns see a reverse bias potential from emitter to base. A reverse bias leakage current must be supplied for each of these bits. For memory products with memory densities in the millions and billions, this reverse current leakage can represent a substantial current drain.
The leakage problem may be further aggravated in the standby mode. A designer may have all the arrays powered up in standby. The arrays are then ready for operation with little wake-up time delay. However, nearly all emitter base junctions of the isolation elements are reverse biased and thus substantial current can flow resulting in power dissipation in the standby mode. This is particularly undesirable for battery powered or power/energy sensitive applications.
Another alternative in the standby mode is to power down all blocks in the standby mode and then power up when the user wishes to read or write. A power up time delay is required due to the need to bias up all the blocks being accessed. Since all rows must be charged up to a voltage at least equal to the programming voltage or the read voltage, this may represent a significant capacitance in large memory arrays, resulting in a significant loss of time and large peak supply current required while awaiting power up.
Thus, it is evident there is a need for better ways to isolate memory cells in phase change memories.